schizoidman@lemmy.mlEnglish · 4 months agoRISC-V NAS: BPI-F3 & OpenMediaVaultplus-squarewww.youtube.comvideomessage-square0fedilinkarrow-up10arrow-down10
arrow-up10arrow-down1videoRISC-V NAS: BPI-F3 & OpenMediaVaultplus-squarewww.youtube.comschizoidman@lemmy.mlEnglish · 4 months agomessage-square0fedilink
schizoidman@lemmy.mlEnglish · 6 months agoBanana Pi BPI-F3: Single-board computer and RISV-V alternative to the Raspberry Pi now availableplus-squarewww.notebookcheck.netexternal-linkmessage-square0fedilinkarrow-up10arrow-down10
arrow-up10arrow-down1external-linkBanana Pi BPI-F3: Single-board computer and RISV-V alternative to the Raspberry Pi now availableplus-squarewww.notebookcheck.netschizoidman@lemmy.mlEnglish · 6 months agomessage-square0fedilink
ylai@lemmy.mlEnglish · 8 months agoAlibaba's research arm promises server-class RISC-V processor due this yearplus-squarewww.theregister.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkAlibaba's research arm promises server-class RISC-V processor due this yearplus-squarewww.theregister.comylai@lemmy.mlEnglish · 8 months agomessage-square0fedilink
ylai@lemmy.mlEnglish · 8 months agoLeaked docs hint Google may use SiFive RISC-V cores in next-gen TPUsplus-squarewww.theregister.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkLeaked docs hint Google may use SiFive RISC-V cores in next-gen TPUsplus-squarewww.theregister.comylai@lemmy.mlEnglish · 8 months agomessage-square0fedilink
gronjo45@lemm.ee · 8 months agoRISC-V Options?plus-squaremessage-squaremessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1message-squareRISC-V Options?plus-squaregronjo45@lemm.ee · 8 months agomessage-square0fedilink
ylai@lemmy.mlEnglish · 9 months ago$99 RISC-V dev board adds Raspberry Pi, Clik board interfacesplus-squarewww.eenewseurope.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-link$99 RISC-V dev board adds Raspberry Pi, Clik board interfacesplus-squarewww.eenewseurope.comylai@lemmy.mlEnglish · 9 months agomessage-square0fedilink
schizoidman@lemmy.mlEnglish · 9 months agoChina bets on open-source chips as US export controls mountwww.reuters.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkChina bets on open-source chips as US export controls mountwww.reuters.comschizoidman@lemmy.mlEnglish · 9 months agomessage-square0fedilink
camel-cdr@beehaw.org · 9 months agoVectorizing Unicode conversions on real RISC-V hardwareplus-squarecamel-cdr.github.ioexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkVectorizing Unicode conversions on real RISC-V hardwareplus-squarecamel-cdr.github.iocamel-cdr@beehaw.org · 9 months agomessage-square0fedilink
ylai@lemmy.mlEnglish · 10 months agoEdge AI chiplet uses SemiDynamics RISC-V coresplus-squarewww.eenewseurope.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkEdge AI chiplet uses SemiDynamics RISC-V coresplus-squarewww.eenewseurope.comylai@lemmy.mlEnglish · 10 months agomessage-square0fedilink
ylai@lemmy.mlEnglish · 10 months agoChina Is All In on a RISC-V Futureplus-squarewww.hpcwire.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkChina Is All In on a RISC-V Futureplus-squarewww.hpcwire.comylai@lemmy.mlEnglish · 10 months agomessage-square0fedilink
ylai@lemmy.mlEnglish · 10 months agoCEO interview: MIPS’ Sameer Wasson on a RISC-V rebootplus-squarewww.eenewseurope.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkCEO interview: MIPS’ Sameer Wasson on a RISC-V rebootplus-squarewww.eenewseurope.comylai@lemmy.mlEnglish · 10 months agomessage-square0fedilink
ylai@lemmy.mlEnglish · 10 months agoMIPS snags top SiFive brains to amp up RISC-V business – Drew Barbier and Brad Burgess join after restructure at former employerplus-squarewww.theregister.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkMIPS snags top SiFive brains to amp up RISC-V business – Drew Barbier and Brad Burgess join after restructure at former employerplus-squarewww.theregister.comylai@lemmy.mlEnglish · 10 months agomessage-square0fedilink
JoeyJoeJoeJr@lemmy.ml · 11 months agoFirst RISC-V mini laptops emergeplus-squarewww.notebookcheck.netexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkFirst RISC-V mini laptops emergeplus-squarewww.notebookcheck.netJoeyJoeJoeJr@lemmy.ml · 11 months agomessage-square0fedilink
testman@lemmy.mlM · 11 months agoRISC V 101 - talks from RISC-V Summitfarside.linkexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkRISC V 101 - talks from RISC-V Summitfarside.linktestman@lemmy.mlM · 11 months agomessage-square0fedilink
Possibly linux@lemmy.zipEnglish · 11 months agoThis CPU is FREE! - Invidiousplus-squareinv.tux.pizzaexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkThis CPU is FREE! - Invidiousplus-squareinv.tux.pizzaPossibly linux@lemmy.zipEnglish · 11 months agomessage-square0fedilink
testman@lemmy.mlM · edit-211 months agoThis CPU is FREE! - LTT video about Milk-Vplus-squarefarside.linkexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkThis CPU is FREE! - LTT video about Milk-Vplus-squarefarside.linktestman@lemmy.mlM · edit-211 months agomessage-square0fedilink
ylai@lemmy.mlEnglish · 11 months agoMeta Sees Little Risk in RISC-V Custom Acceleratorsplus-squarewww.nextplatform.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkMeta Sees Little Risk in RISC-V Custom Acceleratorsplus-squarewww.nextplatform.comylai@lemmy.mlEnglish · 11 months agomessage-square0fedilink
ylai@lemmy.mlEnglish · 1 year agoRISC-V Summit: Ghosts of x86 and ARM Lingerplus-squarewww.hpcwire.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkRISC-V Summit: Ghosts of x86 and ARM Lingerplus-squarewww.hpcwire.comylai@lemmy.mlEnglish · 1 year agomessage-square0fedilink
testman@lemmy.mlM · 1 year agoWhy Nordic is getting involved in RISC-Vplus-squareblog.nordicsemi.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkWhy Nordic is getting involved in RISC-Vplus-squareblog.nordicsemi.comtestman@lemmy.mlM · 1 year agomessage-square0fedilink
schizoidman@lemmy.mlEnglish · 1 year agoVentana's 192-Core RISC-V CPU Takes Aim At AMD Epyc Genoa And Bergamo | Tom's Hardwareplus-squarewww.tomshardware.comexternal-linkmessage-square0fedilinkarrow-up11arrow-down10
arrow-up11arrow-down1external-linkVentana's 192-Core RISC-V CPU Takes Aim At AMD Epyc Genoa And Bergamo | Tom's Hardwareplus-squarewww.tomshardware.comschizoidman@lemmy.mlEnglish · 1 year agomessage-square0fedilink
